Basic Case Simulation -- Thin-Film Transistor (TFT)

GMPT, October 2024

The Thin-Film Transistor (TFT) is one of the most basic and important three-terminal electronic components in the semiconductor industry. Both TFTs and MOSFETs are types of field-effect transistors; however, unlike MOSFETs, TFTs use the same doping type material for the channel, and the gate controls the channel conductivity through a majority carrier accumulation mechanism. We will demonstrate the simulation of a simple structure TFT using the Nuwa TCAD tool and discuss its output and transfer characteristics.

I. Material Parameters

1. Basic Parameters

Material Name	Polycrystalline Silicon (Poly)	Silicon Dioxide (SiO₂)	Molybdenum (Mo)	Glass (Accuglass)
Bandgap/eV	1.169-4.73×10^-4•T²/(T+636.0)	N/A	N/A	N/A
Relative Permittivity	11.9	3.9	13.6	3.9
Electron Affinity/eV	4.17	1	4.9	1
Electron Effective Mass/m₀	0.33	N/A	N/A	N/A
Hole Effective Mass/m₀	0.55	N/A	N/A	N/A
Resistivity/Ω·m	N/A	N/A	5.3476×10^-8	N/A

Default temperature T=300K

2. Models

a. Mobility Model
Low Field: Analytic Low-Field Mobility Model

\mu_0 = \mu_1 \cdot(\frac{T_L}{300})^{\alpha}+\frac{\mu_2 \cdot (\frac{T_L}{300})^{\beta} - \mu_1\cdot(\frac{T_L}{300})^{\alpha}}{1 + (\frac{N}{N_{crit}})^{\delta} \cdot (\frac{T_L}{300})^{\gamma}}

Symbol	Parameter Name	Electron Value	Hole Value	Units
μ₁	mu1	0.005524	0.00497	m²/(V*s)
μ₂	mu2	0.142923	0.047937	m²/(V*s)
α	alpha	0.0	0.0	N/A
β	beta	-2.3	-2.2	N/A
γ	gamma	-3.8	-3.7	N/A
𝛿	delta	0.73	0.70	N/A
N_crit	Ncrit	1.072×10²³	1.606×10²³	m^-3

High Field: Canali Model

\mu=\frac{\mu_0}{\left(1+\left(\mu_0 F / v_s \right)^{\beta}\right)^{1 / \beta}}

v_s = \frac{\alpha}{1+\theta \cdot exp\left( \frac{T_L}{T_{nom} } \right)}

\beta = \beta_0 \cdot \left( \frac{T_L}{300} \right)^{\beta_{exp}}

Symbol	Parameter Name	Electron Value	Hole Value	Units
β₀	beta0	1.109	1.213	N/A
β_exp	betaexp	0.66	0.17	N/A
α	alpha	2.4×10⁵	2.4×10⁵	m/s
θ	theta	0.8	0.8	N/A
T_nom	Tnom	600	600	K

b. Carrier Statistics: Fermi-Dirac distributions
c. Incomplete Ionization Model

II. Structure Setup

1. Substrate and Process Selection

Substrate Material: Glass (Accuglass)

Process:
Step 1: Deposit a layer of polycrystalline silicon (Poly) on the glass substrate
Step 2: p-dope the poly layer, with a concentration of 1×10¹⁸ cm^-3 at both ends and 1×10¹⁴ cm^-3 in the middle
Step 3: Deposit a layer of silicon dioxide (SiO₂) on the poly layer
Step 4: Deposit a layer of molybdenum (Mo) on top of the SiO₂

2. Electrodes

The molybdenum (Mo) serves as the ohmic gate electrode
The polycrystalline silicon (Poly) at both ends serves as the ohmic source and drain electrodes

III. Equilibrium State Solution

The voltages of the gate, source, and drain electrodes are all set to 0V.

IV. Non-Equilibrium State Solution

Transfer characteristics scan: The source voltage is kept at 0V, drain voltage at 5V, and gate voltage increases from -20V to 10V.
Output characteristics scan: The source voltage is kept at 0V, while the gate voltage is fixed at -8V, -10V, and -12V, and the drain voltage increases from 0V to 10V.

V. Simulation Results and Physical Validity Analysis

1. Basic Physical Quantity Distribution

In equilibrium, the central channel has a low p-doping concentration and a low hole concentration, resulting in a non-conductive channel. When a reverse bias is applied to the gate, majority carrier accumulation occurs in the channel, increasing the hole concentration. When the hole concentration reaches a sufficient level, the channel becomes conductive. The following images show the hole concentration distribution in equilibrium and under a reverse gate bias of -10V:


Hole Concentration Distribution in Equilibrium	Hole Concentration Distribution with Reverse Gate Bias (-10V)

2. Characteristic Curves

Transfer Characteristics When the source voltage is 0V, the drain voltage is 5V, and the gate voltage increases from -20V to 10V, a majority carrier accumulation occurs in the channel center when the gate voltage is negative, resulting in a high drain current. As the gate voltage increases, the hole concentration in the channel decreases, and the channel gradually becomes non-conductive. The I_D-V_G curve is shown below:

Output Characteristics When the source voltage is 0V and the gate voltage is set to -8V, -10V, and -12V, the channel is conductive, and the drain current increases as the drain voltage increases. A greater reverse gate bias strengthens the channel’s conductivity. The I_D-V_D curve is shown below:

VI. Conclusion

The simulation results of the Thin-Film Transistor (TFT) using the Nuwa TCAD tool match the expected physical characteristics:

In the transfer characteristic curve, when the gate is forward biased, the hole concentration in the channel center is low, rendering the channel non-conductive with a very small current. Under reverse gate bias, as the bias increases, hole accumulation occurs in the channel center, enhancing conductivity and increasing current.
In the output characteristic curve, under reverse gate bias, the drain current increases with the drain voltage; a stronger reverse gate bias results in a higher drain current.